Index: ucd/ethernat/isp116x-hcd.c
===================================================================
RCS file: /mint/freemint/sys/usb/src.km/ucd/ethernat/isp116x-hcd.c,v
retrieving revision 1.3
diff -u -8 -p -r1.3 isp116x-hcd.c
--- ucd/ethernat/isp116x-hcd.c	15 Feb 2013 17:57:21 -0000	1.3
+++ ucd/ethernat/isp116x-hcd.c	6 Mar 2013 20:41:57 -0000
@@ -87,52 +87,16 @@
 
 #define MSG_MINT	\
 	"\033pMiNT too old!\033q\r\n"
 
 #define MSG_FAILURE	\
 	"\7\r\nSorry, failed!\r\n\r\n"
 
 /*
- * ISP116x chips require certain delays between accesses to its
- * registers. The following timing options exist.
- *
- * 1. Configure your memory controller (the best)
- * 2. Use ndelay (easiest, poorest). For that, enable the following macro.
- *
- * Value is in microseconds.
- */
-#ifdef ISP116X_HCD_USE_UDELAY
-# define UDELAY		1
-#endif
-
-/*
- * On some (slowly?) machines an extra delay after data packing into
- * controller's FIFOs is required, * otherwise you may get the following
- * error:
- *
- *   uboot> usb start
- *   (Re)start USB...
- *   USB:   scanning bus for devices... isp116x: isp116x_submit_job: CTL:TIMEOUT
- *   isp116x: isp116x_submit_job: ****** FIFO not ready! ******
- *
- *         USB device not responding, giving up (status=4)
- *         isp116x: isp116x_submit_job: ****** FIFO not empty! ******
- *         isp116x: isp116x_submit_job: ****** FIFO not empty! ******
- *         isp116x: isp116x_submit_job: ****** FIFO not empty! ******
- *         3 USB Device(s) found
- *                scanning bus for storage devices... 0 Storage Device(s) found
- *
- * Value is in milliseconds.
- */
-#ifdef ISP116X_HCD_USE_EXTRA_DELAY
-# define EXTRA_DELAY	2	/* DEFAULT 2 */
-#endif
-
-/*
  * Debug section
  */
 
 #if 0
 # define DEV_DEBUG	1
 #endif
 
 #ifdef DEV_DEBUG
Index: ucd/ethernat/isp116x.h
===================================================================
RCS file: /mint/freemint/sys/usb/src.km/ucd/ethernat/isp116x.h,v
retrieving revision 1.2
diff -u -8 -p -r1.2 isp116x.h
--- ucd/ethernat/isp116x.h	5 Mar 2013 20:48:34 -0000	1.2
+++ ucd/ethernat/isp116x.h	6 Mar 2013 20:41:58 -0000
@@ -60,19 +60,56 @@
 
 /* --- Board settings -------------------------------------------------------*/
 
 #define ISP116X_HCD_INT_ACT_HIGH
 //#define ISP116X_HCD_INT_EDGE_TRIGGERED
 //#define ISP116X_HCD_SEL15kRES
 //#define ISP116X_HCD_OC_ENABLE
 //#define ISP116X_HCD_REMOTE_WAKEUP_ENABLE
+
 #define ISP116X_HCD_USE_UDELAY
 //#define ISP116X_HCD_USE_EXTRA_DELAY
 
+/*
+ * ISP116x chips require certain delays between accesses to its
+ * registers. The following timing options exist.
+ *
+ * 1. Configure your memory controller (the best)
+ * 2. Use ndelay (easiest, poorest). For that, enable the following macro.
+ *
+ * Value is in microseconds.
+ */
+#ifdef ISP116X_HCD_USE_UDELAY
+# define UDELAY		1
+#endif
+
+/*
+ * On some (slowly?) machines an extra delay after data packing into
+ * controller's FIFOs is required, * otherwise you may get the following
+ * error:
+ *
+ *   uboot> usb start
+ *   (Re)start USB...
+ *   USB:   scanning bus for devices... isp116x: isp116x_submit_job: CTL:TIMEOUT
+ *   isp116x: isp116x_submit_job: ****** FIFO not ready! ******
+ *
+ *         USB device not responding, giving up (status=4)
+ *         isp116x: isp116x_submit_job: ****** FIFO not empty! ******
+ *         isp116x: isp116x_submit_job: ****** FIFO not empty! ******
+ *         isp116x: isp116x_submit_job: ****** FIFO not empty! ******
+ *         3 USB Device(s) found
+ *                scanning bus for storage devices... 0 Storage Device(s) found
+ *
+ * Value is in milliseconds.
+ */
+#ifdef ISP116X_HCD_USE_EXTRA_DELAY
+# define EXTRA_DELAY	2	/* DEFAULT 2 */
+#endif
+
 /* --- ISP116x address registers in EtherNAT --------------------------------*/
 
 #define ISP116X_HCD_ADDR	0x80000016
 #define ISP116X_HCD_DATA	0x80000012
 //#define ETHERNAT_CPLD_CR	0x80000023   /* 0x80000023 - 1 */
 volatile unsigned char* const ETHERNAT_CPLD_CR = (volatile unsigned char*) 0x80000023;
 
 /* --- ISP116x registers/bits ---------------------------------------------- */
Index: ucd/netusbee/isp116x-hcd.c
===================================================================
RCS file: /mint/freemint/sys/usb/src.km/ucd/netusbee/isp116x-hcd.c,v
retrieving revision 1.2
diff -u -8 -p -r1.2 isp116x-hcd.c
--- ucd/netusbee/isp116x-hcd.c	5 Mar 2013 20:48:34 -0000	1.2
+++ ucd/netusbee/isp116x-hcd.c	6 Mar 2013 20:42:02 -0000
@@ -86,52 +86,16 @@
 
 #define MSG_MINT	\
 	"\033pMiNT too old!\033q\r\n"
 
 #define MSG_FAILURE	\
 	"\7\r\nSorry, failed!\r\n\r\n"
 
 /*
- * ISP116x chips require certain delays between accesses to its
- * registers. The following timing options exist.
- *
- * 1. Configure your memory controller (the best)
- * 2. Use ndelay (easiest, poorest). For that, enable the following macro.
- *
- * Value is in microseconds.
- */
-#ifdef ISP116X_HCD_USE_UDELAY
-# define UDELAY		1
-#endif
-
-/*
- * On some (slowly?) machines an extra delay after data packing into
- * controller's FIFOs is required, * otherwise you may get the following
- * error:
- *
- *   uboot> usb start
- *   (Re)start USB...
- *   USB:   scanning bus for devices... isp116x: isp116x_submit_job: CTL:TIMEOUT
- *   isp116x: isp116x_submit_job: ****** FIFO not ready! ******
- *
- *         USB device not responding, giving up (status=4)
- *         isp116x: isp116x_submit_job: ****** FIFO not empty! ******
- *         isp116x: isp116x_submit_job: ****** FIFO not empty! ******
- *         isp116x: isp116x_submit_job: ****** FIFO not empty! ******
- *         3 USB Device(s) found
- *                scanning bus for storage devices... 0 Storage Device(s) found
- *
- * Value is in milliseconds.
- */
-#ifdef ISP116X_HCD_USE_EXTRA_DELAY
-# define EXTRA_DELAY	10	/* DEFAULT 2 */
-#endif
-
-/*
  * Debug section
  */
 
 #if 0
 # define DEV_DEBUG	1
 #endif
 
 #ifdef DEV_DEBUG
Index: ucd/netusbee/isp116x.h
===================================================================
RCS file: /mint/freemint/sys/usb/src.km/ucd/netusbee/isp116x.h,v
retrieving revision 1.3
diff -u -8 -p -r1.3 isp116x.h
--- ucd/netusbee/isp116x.h	5 Mar 2013 20:48:34 -0000	1.3
+++ ucd/netusbee/isp116x.h	6 Mar 2013 20:42:04 -0000
@@ -59,19 +59,56 @@
 
 /* --- Board settings -------------------------------------------------------*/
 
 #define ISP116X_HCD_INT_ACT_HIGH
 //#define ISP116X_HCD_INT_EDGE_TRIGGERED
 #define ISP116X_HCD_SEL15kRES
 #define ISP116X_HCD_OC_ENABLE
 //#define ISP116X_HCD_REMOTE_WAKEUP_ENABLE
+
 //#define ISP116X_HCD_USE_UDELAY
 #define ISP116X_HCD_USE_EXTRA_DELAY
 
+/*
+ * ISP116x chips require certain delays between accesses to its
+ * registers. The following timing options exist.
+ *
+ * 1. Configure your memory controller (the best)
+ * 2. Use ndelay (easiest, poorest). For that, enable the following macro.
+ *
+ * Value is in microseconds.
+ */
+#ifdef ISP116X_HCD_USE_UDELAY
+# define UDELAY		1
+#endif
+
+/*
+ * On some (slowly?) machines an extra delay after data packing into
+ * controller's FIFOs is required, * otherwise you may get the following
+ * error:
+ *
+ *   uboot> usb start
+ *   (Re)start USB...
+ *   USB:   scanning bus for devices... isp116x: isp116x_submit_job: CTL:TIMEOUT
+ *   isp116x: isp116x_submit_job: ****** FIFO not ready! ******
+ *
+ *         USB device not responding, giving up (status=4)
+ *         isp116x: isp116x_submit_job: ****** FIFO not empty! ******
+ *         isp116x: isp116x_submit_job: ****** FIFO not empty! ******
+ *         isp116x: isp116x_submit_job: ****** FIFO not empty! ******
+ *         3 USB Device(s) found
+ *                scanning bus for storage devices... 0 Storage Device(s) found
+ *
+ * Value is in milliseconds.
+ */
+#ifdef ISP116X_HCD_USE_EXTRA_DELAY
+# define EXTRA_DELAY	10	/* DEFAULT 2 */
+#endif
+
 /* --- ISP116x address registers in Netusbee --------------------------------*/
 
 #define ISP116X_HCD_ADDR	0x00FBC000
 #define ISP116X_HCD_DATA	0x00FA0000
 
 /* --- ISP116x registers/bits ---------------------------------------------- */
 
 #define	HCREVISION	0x00